1. Field of the Invention
This invention relates to a data retention circuit and more particularly to a data retention circuit which can securely prevent an erroneous write from destructing data stored in a backup random access memory (RAM) for secure data retention and a game machine provided with the data retention circuit.
2. Description of the Related Art
A conventional video game machine selects a program read from a plurality off program read-only memories (ROMs) or a cassette containing game programs by a chip select signal of an address decoder for desired processing. The address decoder selects one of tile program ROMs containing predetermined programs by a chip select signal. To save data such as the current execution state or the game result intact at any period, the address decoder can select a backup RAM and when a save signal is input, output a backup chip select signal for saving the data at the point in time. Therefore, in the video game machine, the intermediate state or the result (score) of a gate such as a roll playing game can be stored securely.
FIG. 4 shows a schematic circuit configuration of a conventional video game machine.
In FIG. 4, the video game machine is provided with a work RAM 19 and four program ROMs 11 to 14 installed in a cassette attached to a cassette cartridge or the video game machine main unit. Besides the program ROMs 11-14 and work RAM 19, a backup RAM 20 is provided.
An address decoder 21 is provided to select one of the four program ROMs 11-14, work RAM 19, and backup RAM 20; it selects one of the program ROMs 11-14 and work RAM 19 by chip select signals 21a, 21b, 21c, 21d, and 21e respectively. When a predetermined save signal is input, the address decoder 21 outputs a backup chip select signal 21f to enable the backup RAM 20.
A CPU 22 is provided to supply a desired address signal to the address decoder 21 and predetermined address signals to the ROMs 11-14, work RAM 19, and backup RAM 20. Conventional embodiment, a 4-bit address signal is supplied to the address decoder 21 and 8-bit address signals are supplied to the ROMs 11-14, work RAM 19, and backup RAM 20. As is generally known, a data storage RAM 28 is connected to the CPU 22 and an input signal through a joy stick 25 is supplied via an I/O controller to the CPU 22 and further, the operation result is displayed on a CRT 27 through a video controller 28.
Therefore, formerly, in response to a signal entered by the user through the joy stick 25 or a save signal output independently by the CPU 22, the video game machine 10 can select the backup RAM 20 by the backup chip select signal 21f from the address decoder 21 to save, each time, the processing contents made so far.
A software upset or runaway may occur during system execution by the CPU for a reason such as a bug latent in the game programs stored in the program ROMs 11-14 or a shock given to the video game machine 10.
Formerly, a watchdog timer is provided to take a predetermined action or reset the system when such a software upset occurs. If a reset signal is not sent to the watchdog timer every predetermined period, a software upset is judged to have occurred and a predetermined reset processing is performed.
However, when a save signal is input, the conventional video game machine 10 unconditionally selects the backup RAM 20 and saves the state or result at that time. Thus, when a software upset occurs in the system of the video game machine 10, a save signal may be erroneously generated causing the backup chip select signal 21f to be output by accident from the address decoder 21, in which case erroneous data is stored in the backup RAM 20.
Thus, data such as the intermediate state of the game stored is destroyed and reliability of the game machine or the programs used with the game machine degrades.
Particularly, the data which needs to be stored or retained is not frequently written, and if the data is easily lost when the software upset or the like occurs, a fatal loss will be incurred. Prevention of an erroneous write during the software upset is a great problem to be solved.